TODO: Add C code for compiling stuff that will run on the HMX terminal
TODO: Add a photo of the HMX box
As of 2009-11-29 a Linux port is in progress, and is in its early stages. Currently the HMX will download the kernel and boot it (with messages appearing on the screen, no serial support yet) up until it displays the memory map.
At boot time, the kernel memory is laid out in the following order. Due to the MIPS architecture, the following values are offsets into the kernel segments, so you will need to add a value to the offset, such as 0x80000000 for KSEG0, or 0xA0000000 for KSEG1. The memory accessed is the same, the difference is that KSEG0 can be cached whereas KSEG1 cannot.
|0x00001000||Frame buffer (8-bit linear; 0x00 is black, 0xFF is white)|
|0x18000000||Serial port 2 (AUX)|
|0x19000000||Video card registers (see below)|
At boot time the PROM provides a number of services through the SYSCALL interface. The service number is loaded into register $a0.
Service 1: Write character
Input: The lower eight bits of $a1 are of the character to write.
Output: Character written to screen, wrapping to the next line and scrolling if necessary. 0x0A (\r) and 0x0D (\n) can be used.
Service 8: Reinvoke boot monitor
Return to the boot monitor.
The framebuffer is available at offset 0x1000 in kernel memory (e.g. 0xa0001000.) By default the PROM leaves the video data in "mode 13" layout, one byte per pixel.
The display is produced by an AT&T ATT21C505 PrecisionDAC chip, which has its registers memory mapped at offset 0x19000000 (e.g. 0xb9000000.) The register mapping is a little unusual. To convert from a register in table 3 in the datasheet, AD[3:0] are mapped as follows:
offset = (reg << 3) | 1
For example to update the palette you would write the initial colour (say zero) to register 00002, then three bytes per colour (R, G and B) to register 00012. Applying the above formula means register 00002 is at offset 1, and register 00012 is at offset 9. Therefore, you would write the initial colour to memory address 0xb9000001, and the colours byte by byte to memory address 0xb9000009.
It is unknown why the lower three bits have been inserted and what their purpose is (or why the lowest bit must always be set.)
As another example, the monitor can be put into standby by writing the value 65 to memory address 0xb9000031. This sets the "sleep enable" and "SCLK disable during sleep" bits in the CR0 (control #0) register. The control #0 register is at offset 01102 in the datasheet.
Berke Durak's HMX page - if it wasn't for Berke, I wouldn't have figured out half the stuff I did with this and other devices!